Old Intel Xeon servers for plotting: how old is too old?

[codinghorror]

Note that Intel has confirmed advantage; I’ve seen several benchmarks and credible explanations:

@acrosbug

Hi Boba, it’s a CPU architecture limit for both Zen 2 and Zen 3 series. AMD confirmed this back in 2019 that each CCD/IOD link is 32B/cycle for read and 16B/cycle for write. Chia plotting is super write-intensive. For DDR-3600, raw clock 1800MHz * 16B = 28.8Gb/s per CCD. Once your parallel jobs exceed this bandwidth, plot time start to slow down. The only solution is to make DDR4 freq as fast as possible! eg. DDR4-4000

Using PCIE4.0 ssd don’t help much either. Based on current Infinity Fabric design, the DDR4 cannot bring enough write data to the CPU for processing. Intel CPU wins in this part… Ouch